1. Field of the Invention
The present invention relates to a semiconductor apparatus and a manufacturing method thereof.
2. Description of Related Art
A vertical power MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) as a MOSFET for a high pressure is known in the art. As an example of such a power MOSFET, a trench gate MOSFET is well known. This trench gate MOFSFET includes a gate electrode inside a trench with a channel formed in a vertical direction to a principle surface of a semiconductor substrate. This allows a reduction in cell pitch, and highly integrated semiconductor is achieved, and also a low ON-resistance is achieved.
Besides a strong demand in a reduction of manufacturing cost, a lower ON-resistance and a higher destruction resistance are desired as characteristics of such a power MOSFET. The ON-resistance of a power MOSFET should be as small as possible in order to suppress a drop in voltage and increase of heat, for example. Destruction resistance of off-state power MOSFET should be as high as possible for a large voltage.
A conventional semiconductor apparatus disclosed in U.S. Pat. No. 5,072,266 is known, for example. FIG. 25 is a cross-sectional diagram of a conventional semiconductor apparatus disclosed in U.S. Pat. No. 5,072,266.
As shown in FIG. 25, a semiconductor apparatus 800 includes an N type epitaxial layer 902 and a P type base diffusion layer 903 over an N type semiconductor substrate 901. A trench 910 is formed to reach the N type epitaxial layer 902 from the P type base diffusion layer 903. A gate electrode 912 is embedded in the trench 910 via a gate insulating film 911.
A N type source diffusion layer 904 is formed near the trench 910 on the P type base diffusion layer 903. A P+ type diffusion layer 905 is formed between the N type source diffusion layer 904. The P+ type diffusion layer 905 reaches the N type epitaxial layer 902 from a surface of the P type base diffusion layer 903, to a deeper position than the trench 910. The conventional semiconductor apparatus 800 is provided with the P+ type diffusion layer 905 formed deeper than the P+ type diffusion layer 905 so as to improve destruction resistance.
Another conventional semiconductor apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2005-5655 is known. FIG. 26 is a cross-sectional diagram of the conventional semiconductor apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2005-5655.
As shown in FIG. 26, the conventional semiconductor apparatus 900 includes a P+ type diffusion layer 906 below a P type base diffusion layer 903. The P+ type diffusion layer 906 is formed deeper than the trench 910. An N+ type diffusion layer 907 is formed at the bottom of the trench 910. The conventional semiconductor 900 improves destruction resistance by forming the P+ type diffusion layer 906 and the N+ type diffusion layer 907.
However with the semiconductor apparatus 800 shown in FIG. 25, it is necessary to form the P+ type diffusion layer 905 deeper than the trench 910 from the surface of the P type base diffusion layer 903. So, an intensive thermal diffusion is required during manufacturing process. Intensive thermal diffusion causes other diffusion layers to be deeper and to be wider, thereby increasing the width of the semiconductor apparatus 800. Deeper diffusion layers increase ON-resistance. Furthermore larger width of a diffusion layer increases an interval between trenches and a size of a cell, which is a unit region, surrounded by the trenches. This influences a chip size of a semiconductor apparatus, and increases a manufacturing cost.
The conventional semiconductor apparatus 900 shown in FIG. 26 improves destruction resistance by the P+ type diffusion layer 906 formed deeper than the trench 910 and the N+ type diffusion layer 907 formed at a bottom of the trench 910. Destruction resistance could be deteriorated only with the P+ type diffusion layer 906. Electric field can be concentrated to a portion extended to the N type semiconductor substrate 901 side (drain side), as of the P+ type diffusion layer 906, to deteriorate destruction resistance. To prevent a concentration of electric field and improve destruction resistance, both the P+ type diffusion layer 906 and the N+ type diffusion layer 907 are required.
As described in the foregoing, in a conventional semiconductor apparatus, if a P+ type region is formed deeper than a trench from a surface of a P type base layer, size of a cell and manufacturing cost increase. Furthermore without an N+ type layer formed at the bottom of a trench, destruction resistance of a semiconductor apparatus could be deteriorated. Accordingly it has now been discovered that in a conventional technique for realizing a semiconductor device that is a high destruction resistance and a low ON-resistance, there were problems that a configuration of a semiconductor apparatus and a manufacturing method were complicated and the manufacturing cost was increased.